In general, semiconductor manufacturing comprises multiple process steps. As semiconductor integrated circuits (ICs) have continued to increase in complexity, the number of metallization levels, and number of devices on a chip have increased in like manner. Various features within a particular chip often require multiple steps to build. For example, in some cases, multiple lithography, deposition, and planarization steps are required. Each process step adds cost and complexity to the manufacturing process, and may adversely affect overall product yield. It is therefore desirable to reduce the number of process steps required to fabricate a given semiconductor IC.
Features commonly found in semiconductor devices include asymmetric spacers, and buried straps. Asymmetric spacers are used for various functions during semiconductor device manufacturing. For example, if differential offsets are needed for disparate doping requirements of source or drain areas near a gate structure, oftentimes asymmetric spacers are utilized to accomplish this offset. A commonly employed technique for the formation of asymmetric spacers utilizes multiple gate structure sidewall insulator layers and multiple implantations with numerous photoresist masking and etching processes to produce the desired offset. This technique is time-consuming, and the multiple masking and etching steps add to the manufacturing costs accordingly.
Dynamic random-access memory (DRAM) cells are composed of two main components, a storage capacitor that is used to stores electronic charge and an access transistor that is used to transfer the electronic charge to and from the storage capacitor. The storage capacitor may be either planar on the surface of the semiconductor substrate or trench etched into the semiconductor substrate. In the semiconductor industry where there is an increased demand for memory storage capacity accompanied with an ever decreasing chip size, the trench storage capacitor layout is favored over the planar storage capacitor design because this particular setup results in a dramatic reduction in the space required for the capacitor without sacrificing capacitance.
A very important element in the DRAM cell is the electrical connection made between the trench storage capacitor and the access transistor. Such a contact is often referred to in the art as a buried strap formed at the intersection of one electrode of the storage trench capacitor and one source/drain junction of the access transistor.
As the asymmetric spacer and buried strap involve multiple process steps, it is therefore desirable to have an improved method and apparatus for fabrication of these elements, to improve the speed and quality of manufacture for these devices.